Virtual Digital Projects

Cylon Eye
Dynamic Content - push buttons and/or watch lights flash.

Remember the TV show Battle Star Galactica? The Bad Guys were robots that had an "eye" that went back and forth. This project presents two versions of the eye. A simple introduction to Multi Media Logic and the schematic capture facility.

Second and third page of the circuit.

Theory of Operation
Flip Flops and Counter
	Pictured on the left are a D-Type Flip Flop, Set/Reset (S/R) Flip Flop, J-K Flip Flop and a 4-Bit Counter. In general, inputs to these devices appear on the left and top, while their outputs are on the right. In the case of the Flip Flops, there are two outputs -- "Q" and not "Q". The "Q" appears above the not "Q" on each device, and the not "Q" features a bar over the "Q". The Counter has five outputs on its right side. The lower four constitute a 4 bit number, with the most significant bit (labled 3) on top, and the lowest significant bit (labled 0) on the bottom. The upper one (labled C) is a carry output. All Flip Flops start in the "Unknown" state when the Multimedia Logic simulation is begun.This means both "Q" and not "Q" output "Unknown", The Counter starts the simulation with all four count bits and Carry output at "0".

Flip Flop and Counter Clock Inputs
	Pictured on the left are the D-Type Flip Flop, J-K Flip Flop and the 4-Bit Counter.with their Clock Inputs circled. Each of these devices react differently when their clock inputs go from "0" to a "1" state (positive going edge).

Reset Pulse Generator
	At the start of the simulation, the Q output of the 1st Stage Flip Flop is in the "Unknown" state, and is fed into a node. This particular node changes the "Unknown" state into the "0" state, which then drives the D input of the 2nd stage Flip Flop. The "Unknown" Q output of the second stage drives another node and is also changed to the "0" state, which drives the ~Reset (read: not Reset) Signal Sender to the "0" state. Also, the not Q output (the lower Q with a bar over it) of the second stage Flip Flop drives a third node which changes any "Unknown" input to "1" and then drives the Reset Signal Sender to the "1" state.
When the Reset signal is asserted, the Flip Flop in the Time Base and the four bit Counter are cleared. In the case of the Counter, all outputs become a "0" state, and in the case of the Time Base Flip Flip, its Q output becomes "0" and its not Q output becomes a "1". Meanwhile, the Oscillator outputs a positive going edge every twenty simulation cycles, and drives the clock input of both 1st and 2nd stage Flip Flops. On the first positive going edge of the Oscillator output, the 1st stage Flip Flop clocks the Constant "1" connected to its D input to its Q output. The 1st stage Flip Flop has now done its job for the circuit, and will not change state again for the rest of the simulation run. Also on the first positive going edge of the Oscillator output, the 2nd stage Flip Flop -- which has a "0" on its D input -- will transfer that "0" to its Q output (which used to output "Unknown"), and a "1" to its not Q output (which also used to output "Unknown"). Since the node on the Q output is already driving the ~Reset Signal Sender to a "0" state, and the node on the not Q output is driving the Reset Signal Sender to a "1" state, there is no change of the Reset signal, and thus remains asserted. With the D input of the 2nd stage Flip Flop now a "1", the next positive going edge of the Oscillator output will cause its Q output to change to a "1" state, and its not Q output to change to a "0" state. The 2nd stage Flip Flop has now done its job for the circuit, and will not change state again for the rest of the simulation run. With the 2nd stage Flip Flop in the "1" state (Q outputs "1" and not Q outputs "0"), the Reset signal is unasserted. This allows the Counter to begin counting and allows the Time Base Flip Flop to respond to its clock input.

Time Base

The Timer produces a steady stream of pulses on its "Z" output at 20 Hz (cycles per second). As long as the Reset signal is asserted, ~Reset will be "0", and the asynchronous not CLR input of the J-K Flip Flop forces it into a "0" state ("0" on the Q output, "1" on its not Q output). The Reset Pulse Generator is responsible for asserting Reset and ~Reset for the first fourty simulation cycles of each run. Once the ~Reset is unasserted (goes to a "1" state), the positive going edge from the Timer will cause the J-K Flip Flop to change from the "0" state to the "1" state. On each subsequent positive going edge of the Timer "Z" output, the Time Base Flip Flop will Toggle states (that is, go from the "0" state to the "1" state, or go from the "0" state to the "1" state.), producing a square wave on the 10Hz Signal Sender.

CYLON Eye One
At the start of the simulation run, all these "D-Type Flip Flops" (FF1 through FF6) will be in the "Unknown" state (both Q and not Q output "Unknown"). The "Unknown" from the not Q output of FF6 comes out of the "Unknown" to "1" node as a "1" state. (Tie-Point nodes never change the signal they pass) On the first positive going edge of the 10Hz signal, FF1 transfers the "1" on its D input to its Q output. FF2 through FF6 do not change. On the second positive going edge of the 10Hz signal, FF1 does not change, but FF2 transfers the "1" it now sees on its D input from FF1 to its Q output. FF3 through FF6 remain unchanged. On the third positive going edge of the 10Hz signal, FF1 and FF2 do not change, but FF3 transfers the "1" it now sees on its D input from FF2 to its Q output. FF4 through FF6 remain unchanged. On each successive positive going edge of the 10Hz signal, FF4, FF5, and FF6 will, in its turn, transfer a "1" to its Q output. When FF6 has its turn, it will change its not Q output from "Unknown" to "0". This, in turn, is fed back to the "D" input of FF1 On the seventh positive going edge of the 10Hz signal, FF1 will transfer the "0" on its D input to its Q output. Then, on each successive positive going edge of the 10Hz signal, FF2 through FF6 will, in its turn, transfer a "0" to its Q output, and thus changing state. When FF6 sees a "0" on its D input, it transfers "1" to its not Q output, which will change the D input of FF1 to "1", causing it to transfer a "1" to the D input of FF2 Thus, the cycle repeats, with "1", then "0", then back to "1", etc., for the duration of the simulation run.

CYLON Eye Two
At the start of the simulation run, the Set/Reset (S/R) Flip Flop is in the "Unknown" state (Both Q and not Q output "Unknown") During the first fourty simulation cycles, the Reset signal is asserted to the "1" state by the Reset Pulse Generator circuit. This forces the 4-Bit Binary Up/Down Counter to output all "0's". When the 3 to 8 line Demultiplexor sees a 0 from the Counter, it will output "0" on its 0 output line, and a "1" on output lines 2 through 7. The "0" from the 0 output of the Demultiplexor is changed to "1" by the connected Inverter Thus, the Signal Sender marked F0 is driven to a "1", causing the Signal Receiver marked F0 to apply a "1" to the Reset (R) input S/R Flip Flop. The S/R Flip Flop in turn applies a "0" to its Q output. The other outputs of the Demultiplexor are changed to "0" by their respective Inverters When the Reset signal is finally unasserted, the Counter will respond to its clock input. Because Set/Reset (S/R) Flip Flop now outputs "0" on its Q output, the Counter's D input (Direction) is also "0". When the D input is at "0", it counts up in binary. On the first positive going edge of the 10Hz signal, the Counter goes from 0 to 1. A count of 1 on the 3 input lines of the Demultiplexor causes a "0" to be output on its 1 line, and a "1" to be output on all the other lines. On each successive positive going edge of the Counter's C input, the Counter's output goes up, and the Demultiplexor will see on its inputs 2, 3, 4, and 5. It will in turn put a "0" on the corresponding output line: 2, 3, 4 and 5, while holding all the others at a "1". (No two output lines of the Demultiplexor will ever be "0" at the same time.) When the 5 output line goes to a "0", the connected Inverter changes it to a "1", which is fed back through the F5 Signal Sender/Receiver pair to the Set/Reset (S/R) Flip Flop S input, causing it to transfer a "1" to its Q output. When the Q output of the Set/Reset (S/R) Flip Flop changes to "1", the Direction input of the Counter also changes, and begins counting down from 5 to 4, then 3, then 2, then 1 and then 0. When the Demultiplexor sees a 0 on its three input lines from the Counter, it causes its 0 output line to again go to "0", which is changed to a "1" by the Inverter and passed through Signal Sender/Receiver pair F0 back to the R input of the Set/Reset (S/R) Flip Flop. When the Set/Reset (S/R) Flip Flop R input sees "1", the Q output changes to "0". When the Set/Reset (S/R) Flip Flop Q output goes to "0", the Counter's D input sees "0", and the Counter begins counting up from 0 to 1, then 2, then 3, then 4, and then 5. Thus, the cycle repeats, as the Counter counts up to 5, then counts down to 0, then back up to 5 again, for the duration of the simulation run.

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